1. Field of the Invention
The present invention relates to a thermosetting resin composition, a dry film including the thermosetting resin composition, and a multilayer printed wiring board including the thermosetting resin composition.
2. Discussion of the Background
As a process for producing a multilayer printed wiring board, a production technique of buildup method that an organic insulation layer and a conductor layer are alternately built up on the conductor layer of an inner layer circuit substrate has been paid to attention in recent years. For example, there is proposed a process for producing a multilayer printed wiring board that an epoxy resin composition is coated on a circuit-formed inner layer circuit substrate and heat cured, then a concave-convex roughened surface is formed on the surface by a roughening agent, and a conductor layer is formed by plating (see Japanese Unexamined Patent Publication 07-304931 and Japanese Unexamined Patent Publication 07-304933). Further, there is proposed a process  for producing a multilayer printed wiring board that an adhesion sheet of an epoxy resin composition is laminated on a circuit-formed inner layer circuit substrate and heat cured, then a concave-convex roughened surface is formed on the surface by a roughening agent, and a conductor layer is formed by plating (see Japanese Unexamined Patent Publication 11-87927).
A process for producing a multilayer printed wiring board by a conventional buildup method will be explained as an example with reference to FIG. 1; first, outer layer conductor patterns 8 are formed on both sides of a laminated substrate X that an inner layer conductor pattern 3 and a resin insulation layer 4 are previously formed on both surfaces of an insulation substrate 1, on which an epoxy resin composition is coated by a suitable method such as screen printing method, splay coating method and curtain coating method, then heat cured, thereby to form a resin insulation layer 9. (In the case of using a dry film or prepreg, it is heat cured by lamination or hot plate press to form a resin insulation layer 9.)
Subsequently, a through-hole 21 penetrating a resin insulation layer 9 and a laminated substrate X, and a via hole (not shown) for electrically connecting connection parts in each conductor layer are formed. Boring can be conducted by a suitable means such as drill, mold punch and laser light. Thereafter, roughening of each resin insulation layer 9 using a roughening agent and desmear of hole parts are conducted. In general, roughening treatment of the cured coating of an epoxy resin composition on an inner layer circuit substrate is conducted as follows; the entire surface of the cured composition is swelled with an organic solvent such as N-methyl-2-pyrrolidone, N,N-dimethylformamide and methoxypropanol, or an alkaline aqueous solution such as sodium hydroxide and potassium hydroxide, and roughened using an oxidant such as bichromate, permanganate, ozone, hydrogen peroxide/sulfuric acid and nitric acid.
Next, a conductor layer is formed on the surface of resin insulation layer 9 by nonelectrolytic plating, electrolytic plating, or a combination of nonelectrolytic plating and electrolytic plating. The process for forming a conductor layer by nonelectrolytic plating is a  process where the entire surface of the cured composition is immersed in an aqueous solution containing a catalyst for plating to adsorb the catalyst, then, immersed in a plating solution to precipitate plating. The conductor layer in this case is coated not only on the surface of resin insulation layer 9 but also coated on the whole surface in the through-hole 21 and blind holes. Subsequently, in accordance with a common method (subtractive method, semi-additive method, and the like), a predetermined circuit pattern is formed in a conductor layer on the surface of resin insulation layer 9 to form an outermost layer conductor pattern 10 on both sides as shown in FIG. 1. In this case, a plating layer is also formed in the through-hole 21 as described above, as a result, a connection part 22 of outermost layer conductor pattern 10 and a connection part 3a of inner layer conductor pattern 3 of the multilayer printed wiring board are electrically connected, and a through-hole 20 is formed. Further, in the case of producing a multilayer printed wiring board, the resin insulation layer and conductor layer may alternately be built up. Additionally, in the buildup, an example of forming the resin insulation layer and conductor layer on the laminated substrate has been explained, but in place of a laminated substrate, a single-sided substrate or a double-sided substrate may be used.
As described above, as a composition used for forming an interlayer insulation layer of a multilayer printed wiring board, an epoxy resin composition is generally used. However, since cured coatings of the conventional epoxy resin composition are difficult to form a good concave-convex roughened surface by roughening treatment, there has been a problem that adhesion strength to a conductor layer is low.
Further, in accompanying with the development of miniaturization and high performance of electric appliances, buildup layers in a multilayer printed wiring board are multilayered, there have been increasing demands of a multilayer printed wiring board having a multi-via structure called a staggered via or a stacked via that a via hole is connected across a plurality of buildup insulation layers. In the multilayer printed wiring board having such multi-via structure, since  coefficients of thermal expansion of copper wiring for connecting via holes and an insulation layer are markedly different, when reliability tests such as thermal cycle are carried out, there has been posed a problem that copper wiring or an insulation layer is cracked.
Then, in order to suppress the coefficient of thermal expansion of a resin composition composing an insulation layer low and to enhance peel strength (peeling strength) of a conductor layer formed by plating, there has been proposed a resin composition for interlayer insulation of a multilayer printed wiring board (see Japanese Unexamined Patent Publication No. 2005-154727) as follows: it comprises (a) an epoxy resin being liquid at a temperature of 20° C. having an epoxy group of two or more in a molecule, (b) a solid epoxy resin of aromatic series having an epoxy group of three or more in a molecule and an epoxy equivalent of 200 or less, (c) a phenol series curing agent, (d) at least one resin having a glass transition temperature of 100° C. or more selected from the group consisting of a phenoxy resin, a polyvinyl acetal resin, a polyamide resin and a polyamideimide resin, wherein the ratio of the component (a) and component (b) to the epoxy resin is 1:0.3 to 1:2 in weight ratio, the ratio of an epoxy group in the resin composition to a phenolic hydroxyl group in the phenol series curing agent of component (c) is 1:0.5 to 1:1.5, and the content of the resin of component (d) is 2 to 20% by weight of the resin composition.
As the resin composition for interlayer insulation, by containing two kinds of epoxy resins of liquid epoxy resin and solid epoxy resin and a phenoxy resin, and the like having a glass transition temperature of 100° C. or more, the coefficient of thermal expansion of the resulting thermosetting resin composition can be suppressed low. However, in a state before curing (dry coating, dry film and prepreg), although measurements by an Erichsen tester at low test speed show relatively high values, measurements show low values at high test speed because the compound ratio of a solid epoxy resin is low, so a point to be improved on handling in processing a board has been left yet. 
The contents of Japanese Unexamined Patent Publication 07-304931, Japanese Unexamined Patent Publication 07-304933, Japanese Unexamined Patent Publication 11-87927, and Japanese Unexamined Patent Publication No. 2005-154727 are incorporated herein by reference in their entirety.